1. Field of the Invention
The present invention relates generally to the field of parallel graphics processing and, more specifically, to sharing a data crossbar for reads and writes in the data cache.
2. Description of the Related Art
A graphics processing unit (GPU) is a specialized processor that is configured to efficiently process complex graphics and other numerical computations. Each GPU has several on-chip hardware components, such as memory caches and logic operations units, configured to efficiently perform the graphics and numerical computations.
In a typical GPU, hardware components communicate with one another over a crossbar configured to transmit different types of traffic. A crossbar is typically designed to transmit traffic in serial manner, where a particular packet of data is transmitted to a destination component once all previously received packets of data have been delivered. Such a design of the crossbar often results in packets of data that have a high priority to be stalled behind previously-stalled packets of data. In addition, some components transmit and/or request data that is required to be transmitted with a fixed latency. In a design, where all packets of data are processed in a serial manner, such a requirement cannot always be met.
As the foregoing illustrates, what is needed in the art is a mechanism for transmitting data between different on-chip hardware components without causing blocks or deadlocks.